Learning Nios II Embedded Processor

For those who have joined the advanced embedded workshop on Nios II, the following items might be helpful

• Our facebook group: https://www.facebook.com/groups/esddn/
• Our yahoo group: http://groups.yahoo.com/group/esdd_heqep/

• A beginners tutorial on Nios II: Click Here

• Nios II documentations: Click Here

• Source Code Example for using Nios II with SDRAM on DE1: Click Here
• Note: This example uses PLL to keep the phase of SDRAM clock 3ns ahead of the processor clock. To learn how to create and use a PLL in Quartus II, Click Here
• The PLL was created in a wizard and the module of the pll was called in the main module of the verilog code.
• All the files are given, if you can't open the Eclipse project, just start a new application & bsp from template and choose hello world. The required sopcinfo file is also available in the zip archive.
• You might get an system timestamp mismatch error. In that case, just regenerate the nios 2 processor design in qsys, recompile in quartus, reprogram the FPGA from quartus, regenerate bsp in eclipse, build and run again.
• If you get errors regarding makefile in eclipse, use the option Clean project in the context menu that appears after right clicks.
• Finally if you can't eradicate the Timestamp Mismatch errors, just check the Ignore Timestamp Mismatch option in the dialogue box that appears and click run.

• C Code example for (Eclipse) using LCD using Character LCD Controller (From Qsys Library): Click Here

Additional Links:

• DE2-115 System Builder
• DE1 Pin Assignment file for importing assignments.